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• Support Resources

• Generators with a DVI or HDMI output now support a "hot-plug formats" special mode, which configures the Format knob to list only formats reported by the EDID structure from the connected DVI or HDMI display. This format knob list is created automatically when a DVI or HDMI display is connected with the generator. To active this mode, hold down R and ASC while starting the generator, or use the SROP 16384 command. To switch between the EDID-based knob list and the standard knob list, hold down the R button while pressing and releasing the ACS button.
  
  

  When the generator is connected with a DDC-compliant analog display, holding down R while pressing and releasing the ACS button configures the knob list for the display.

• Added AFDtest image, which work in analog and digital modes. The AFDtest image demonstrates different aspect ratios and content maps. See the HDMI manual (update available soon) for more information.
  
  
• Added PixelRep image, which works with EIA/CEA-861B formats in both analog and digital modes. The PixelRep image can be used to apply pixel repetition after the format is loaded. Use the image to vary the number of pixels-per-pixel to render the image with repeated pixels for test purposes. For more information about pixel repetition, see the EIA/CEA-861B standard.
  
  
• The EdidData image now reads and parses the first timing extension block.
  
  
• Generator can load an 8-bit image (.bmp) directly from a PCMCIA card (instructions).

• Corrected short broad pulse delay for the 720p formats in analog mode.

• When using analog HDTV formats with tri-level sync type, the TSPG command and query can toggle between tri-level and bi-level syncs. The Bilevel, Trilevel Toggle key operation can also be used to toggle the tri-level and bi-level sync types (see the GenOps image for instructions).
  
  
• New Australian formats:
  
  

  576i50	SD @ 100Hz field rate HRAT=31250 VTOT=625 SCAN=2
  1152iSH	AS 4933.1-200X (8/5 vertical scope 720 to 1152)
  1152iSH_	1152iSH at harmonic of SMPTE 274M 148.5MHz
  1152iLH	AS 4933.1-200X (6.7% letterbox 1080 in 1152)
  1152iLH_	1152iLH at harmonic of SMPTE 274M 148.5MHz
  576i50WL	SD letterboxed in 576i50W
  576i50_L	576i50WL at harmonic of SMPTE 274M 148.5MHz
  576i50WH	HD @ 100Hz field rate HRAT=31250 VTOT=625 SCAN=2
  576i50_H	576i50WH at harmonic of SMPTE 274M 148.5MHz
  576pWL	SD letterboxed in 576pWH
  576pWL_	576iWL at harmonic of SMPTE 274M 148.5MHz
  576pWH_	576pWH at harmonic of SMPTE 274M 148.5MHz
  1152iLA	SD 2/1 vertical scope 576 to 1152 & letterboxed in 1188
  1152iLA_	1152iLA at harmonic of SMPTE 274M 148.5MHz

  
  
  

• The DDC auto-configuration (toggling R and ACS keys) now creates a format knob list that has all the detailed timings supported in the EDID data of the receiver. Previously, only the first timing was added to the knob list.
• Digital-friendly mode is supported on generators with an LVDS daughter card.

• The DVI receiver now supports CEA-861 EDID timing extension version 1, which has two, 128-btye blocks. Below are supported formats.

  Standard VESA formats:

  • 720 x 400 @ 70Hz IBM0770H @ 28.40 Mpixel
  • 720 x 400 @ 88Hz XGA2 @ 35.50 Mpixel
  • 640 x 480 @ 60Hz DMT0660 @ 25.20 Mpixel
  • 640 x 480 @ 67Hz APP0667 @ 31.30 Mpixel
  • 640 x 480 @ 72Hz DMT0672 @ 31.50 Mpixel
  • 640 x 480 @ 75Hz DMT0675 @ 31.50 Mpixel
  • 800 x 600 @ 56Hz DMT0856 @ 36.00 Mpixel
  • 800 x 600 @ 60Hz DMT0860 @ 40.00 Mpixel
  • 800 x 600 @ 72Hz DMT0872 @ 50.00 Mpixel
  • 800 x 600 @ 75Hz DMT0875 @ 49.50 Mpixel
  • 832 x 624 @ 75Hz APP0875 @ 55.00 Mpixel
  • 1024 x 768 @ 87Hz DMT1043 @ 44.90 Mpixel
  • 1024 x 768 @ 60Hz DMT1060 @ 65.00 Mpixel
  • 1024 x 768 @ 70Hz DMT1070 @ 75.00 Mpixel
  • 1024 x 768 @ 75Hz DMT1075 @ 78.75 Mpixel
  • 1280 x 1024 @ 75Hz DMT1275G @ 135.0 Mpixel
  • 1152 x 870 @ 75Hz APP1175 @ 100.0 Mpixel

  Detailed timings:

  • 1600 x 1200 @ 60Hz DMT1660 @ 162 Mpixelz
  • 1280 x 1024 @ 60Hz VSC1260G @ 108 Mpixel

  EIA/CEA-861-B formats:

  • 720x480 progressive at 59.94Hz and 27Mhz and 4:3
  • 720x480 progressive at 59.94Hz and 27MHz and 16:9
  • 1280x720 progressive at 50Hz and 74.25MHz and 16:9
  • 1280x720 progressive at 60Hz and 74.25MHz and 16:9
  • 1920x1080 interlace at 50Hz and 74.25Mhz and 16:9
  • 1920x1080 interlace at 60Hz and 74.25MHz and 16:9
  
  
  
• The generator now verifies PCMCIA SRAM cards after writing data. If the card is bad, Card is bad is displayed for 3 seconds.
• The EdidData image displays the hex sheet for the two blocks in case there is an extension block. Also, if the check sum is bad, the EdidData image displays the check sum value that should be used.
• Added -4% gray level to the SMPTEbar image.

• The "passed" message used with HDCP images now displays in the correct font.
• Corrected analog output level of the red color when the AVSS command is used to control the voltage levels of the colors.
• Corrected errors reported by the DeltaErr image on the DVI analyzer when using format TEST165.
• VGM 3.01 does not recognize some format parameters, including the digital video quantization modes (DVQM), and the number of bits per color component (NBPC). Using VGM to edit a TV format could cause the DVQM and NBPC parameters to be set to wrong values when the format is saved in the generator. These parameters are now stored correctly, and are not changed by VGM.
• Corrected low DVI output voltage level with HDCP images on generators with a BroadCom transmitter.

• The HdcpA1B1, HdcpA1B2, HdcpA2B1, HdcpA2B2 and HdcpProd images now display error codes for 2 seconds before retrying. These images also check if a receiver is present before starting the HDCP process.
• Corrected errors related to running patch mode for the DVI analyzer at Test165 format with stand still images.
• Corrected how DVI analyzer reads pixel values with interlaced formats.

• Added two new patterns to graphics library. trump1 has the following repeated pattern:
  

  1010
  1010
  0101
  0101
  

  trump2 has the following repeated pattern:

  1010
  0101
  0101
  1010
  

• Added HalfClk image, which has alternating values of pixels with colors (R=1, G=1, B=1) and (R=255, G=255, B=255). This image generates square signals at half pixel rate at the DVI outputs.
• Digitial friendly mode is allowed only if the generator has the digital option.

• Reduced size of moving boxes in the persist image.
• Centered text in the GenStats and GenOps images.

• Added commands that read and write control signals for DVI transmitters.

  Quantum Data digital generators use either a BCM7500 (BroadCom) or a Sil 170B (pin compatible with Sil 168) DVI transmitter. Control signals for the BCM7500 and the Sil 170B transmitters are defined differently. To identify the transmitter in your generator, load the GenStats image. If DVI (SII) is displayed under Options, the generator has an Sil 170B transmitter. If DVI is displayed, the generator has a BCM7500 transmitter.

  The SCTL command sets the control signals of the DVI transmitter to HIGH. The RCTL command resets the control signals of the transmitter to LOW.

  The SCTL? and RCTL? queries read the status of the control signals from generators with an Sil 170B transmitter. You cannot read the status of the control signals from a BCM7500 transmitter.

  The BCM7500 has 8 dedicated pins for these control signals, 4 pins for each link. CTL00 (pin 96), CTL01 (pin 93), CTL02 (pin 92), and CTL03 (pin 91) are used for link zero. Also, CTL10 (pin 75), CTL11 (pin 74), CTL12 (pin 71) and CTL13 (pin 70) are used for link one.

  The SCTL and RCTL commands take one parameter, a single byte in hex. Each bit corresponds to a control pin, making the value a mask. The least significant bit is associated with CTL00, and the most significant bit with CTL13. The SCTL command sets the bit with value "1" to HIGH. The RCTL command sets the bit with value "1" to LOW.

  The mask is as follows:

  [CTL13 CTL12 CTL11 CTL10 CTL03 CTL02 CTL01 CTL00]

  Examples for BCM7500 transmitter:

  1. Set only CTL01 and CTL11 pins to HIGH:

  R:\>SCTL 22

  2. Set only CTL02 and CTL10 pins to HIGH:

  R:\>SCTL 14

  3. Reset only CTL02 and CTL10 pins back to LOW:

  R:\>RCTL 14

  4. Reset CTL00 and CTL12 pins back to LOW:

     R:\>RCTL 41

     Note that CTL03 and CTL13 are not affected by these commands since these two pins are used for HDCP control.

An Sil 170B transmitter has two control signals, CTL1 and CTL2, which are controlled through the I²C bus on the Sil 170B. The commands described above can also control these signals by using the least significant 2 bits in the byte, and ignoring the other bits.

Examples for Sil 170B transmitter:

1. Set CTL1 to HIGH:

R:\>SCTL 01

2. Set CTL2 to HIGH:

R:\>SCTL 02

3. Set both CTL1 and CTL2 to HIGH:

R:\>SCTL 03

4. Reset CTL2 to LOW:

R:\>RCTL 02

For the SiI 170B, use the RCTL? or SCTL? query to read the status of these two signals.

After running the commands above, the following query would return 01:

R:\>RCTL?

• Added support for reading the enhanced display data channel (DDC) using the I²C bus. All parameters are hex values.

  i2cr? e_ddc ddc_addr1 segment_num ddc_addr2 offset bytes

  This example returns the 128 bytes of Extended Display Identification Data (EDID) data from the monitor:

  i2cr? e_ddc 60 0 a0 0 80

• Added support for new Quantum Data video standards.
• For the DDC auto-configuration, the format created from the first detailed timing is now assigned the gamma, sync swing, and video swing values from the EDID data. Previously, it was set to no gamma, and the swings were 700mV and 300mV. The vertical total also has been corrected for interlace formats, since the EDID detailed timing returns the values for one field while the format requires the values for one frame (for example, two fields).
• Added standard colors gray -2% and gray -4%, which are blacker than black. The SMPTEbar image uses these colors.
• The GraysAll image now displays the gray level.

• When using the HDCP tester mode with a sequence that contains an HDCP image (HdcpA1B1, HdcpA1B2, HdcpA2B1, HdcpA2B2, or HdcpProd), you no longer need to press the Step button to proceed with the HDCP testing.

• Added the following commands to read and write the VESA DDC/CI (DDC2Bi) using the I²C bus. All parameters are hex values.

  i2cw ddcci dst_addr src_addr count [command+data+chk_sum]

  Use no spaces between the command, data, and chk_sum parameters.

  i2cr? ddcci dst_addr bytes

This example is from page 13 in the VESA DDC/CI specification:

i2cw ddcci 6E 51 81 B10F
i2cr? ddcci 6F 5

This example is from page 16 in the VESA DDC/CI specification:

i2cw ddcci 6E 51 85 C0XXXXXXXXCH
i2cr? ddcci 6F 7

• The AVSS (analog video signal swing) command now controls the video swing on the TV for generators with an ADV7194 chip. To identify the TV chip in your generator, load the GenStats image. If TV(AD) is displayed under Options, the generator has an AD7194 chip. If TV is displayed, you have the an HMP8154 chip, which cannot control the video swing.

• Corrected vertical pulse for progressive European separate sync formats. The vertical pulse was off by one half line and short by one line.
• Updated HDCP? query to test HDCP functionality with any static image. The query allows you to choose the key that is used (test or production) and the length of time that the HDCP test stays enabled. For more information, see knowledge base article 100145.

• Added commands to control the DVI analyzer remotely. More information about analyzer commands.
• Added a parameter to the HVPD command and HVPD? query to write and read the pixel delay between the horizontal and vertical pulse. If no value is specified, the default value is 0.

• Creating custom fonts (maps) used with the FocusMxx images to generate a full screen of that font (special character, map) now works correctly. For more information, see knowledge base article 100149.
Corrected the DC offset of the TV output when the generator is turned on with a TV format loaded.

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