• 7.48127100
• 7.48127000
• 7.48126400
• 7.48126000
• 7.48123000
• 7.48120000
• 7.48119100
• 7.48119000
• 7.48117500
• 7.48117400
• 7.48116400
• 7.48116200
• 7.48116100
• 7.48115000
• 7.48114000
• 7.48112000
• 7.48111000
• 7.48100000
• 7.38190000
• 7.38180000
• 7.38150000
• 7.38140000
• 7.38130000
• 7.38120000
• 7.38100000
• Support Resources

This firmware provides the following new features:

• No new features were added with this release.

This firmware corrects the following anomolies:

• Miscellaneous corrections to the EDID HDMI compliance test.

This firmware provides the following new features:

• Now includes Lipsync image for testing synchronization between audio and video. Select the lipsync image with the Image knob or the command line with IMGL lipsync;IMGU. This image has several subimages that enable you to vary the interval.
• Now includes TSTMusic image for testing audio.
• Now includes CECTest image for testing a CEC sink device. The CECTest image queries the connected CEC device for its physical address and the Vendor ID.

This firmware corrects the following anomolies:

• Audio parameters queried and set through the command line and appearing on images are now consistent
• Analyzer function now shows the hsync and vsync parameters offset on the FormatRx image.

This firmware provides the following new features:

• Now includes the CEA-861-C formats.
• Now includes the VESA Coordinated Video Timing (CVT) formats.

This firmware corrects the following anomolies:

• Pedestal now appears correctly on the composite output.
• 32kHz sampling rate on HDMI outputs has been corrected.
• Self calibration program was corrected to eliminate drift and incorrect setting of default values.
• PAL-60 and NTSC44 formats for the new TV chip (ADV7192) have been corrected.

Note: Also requires ADV7192 chip installed on video board which can be identified on the genstats image under options, e.g.: TV(AD7192)

This firmware provides for the following features and fixes:

• Support for the new TV chip (ADV7192) which fully supports the PAL-60 format.

Note: Also requires ADV7192 chip installed on video board which can be identified on the genstats image under options, e.g.: TV(AD7192)
• Corrects a deficiency in the EDIDHDMI image that did not recognize all DTDs and SVDs in a display's EDID.
• Enables full support for HDCP when generator Tx is connected to a repeater.

This firmware provides for the following features:

• Full single link HDMI transmitter up to 165MHz
• HDMI Analyzer (receiver) up to 150MHz
• 8 channel HDMI audio supported through new images: Audio_1, Audio_1f, through Audio_8, Audio_8f
• Additional HDMI audio sampling rates supported: 32, 44.1, 48, 88.2, 176.4 and 192KHz
• Support for HDCP 1.1 repeater testing

• RGBW command now allows for different depth of each color at the analog DACs.
• Support for HDMI FPGA revision B.

This is the latest firmware release that you can upgrade to if you have a generator with the Broadcom DVI transmitter which can be identified by looking at the genstats image. On the genstats image the Broadcom DVI transmitter will be indicated by a revision AD or AF of the DVI daughter board.

• Updated to enable gateware updates using serial interface.

• (DVI and HDMI only) Added DV_Swing image, which can be used to temporally change the digital video swing (DVSS format parameter) between 90 and 1620 mVp-p of the HDMI and DVI digital output for the active format. This image displays the current video swing value over a graduated (ramp) background. To adjust the swing in 4 mV increments, press the Step key, then turn the Image knob. Press the Step key again to reset the digital swing value to the default value, which is 1000 mVp-p for all formats. This image is supported by compliant HDMI boards (revision F or later), and DVI boards with FPGA F1 or later. Note: The DVSC command can be use to set the swing value between 150 and 1500 mVp-p.
• (HDMI analyzer only) Added CDF_Sink and EdidHDMI images, which provide pass/fail tests of tests 8-1, 8-2, 8-3, 8-17, 8-18 and 8-19 in the HDMI Compliance Test Specification 1.0.
• (HDMI analyzer only) With the HDMI analyzer installed, the generator can automatically output derivations, required by tests 8-19 and 8-20 in the HDMI Compliance Test Specification 1.0, of each base format supported by the device under test. For each supported base format, the generator creates formats with 4:2:2 and 4:4:4 sampling, and formats with the minimum and maximum pixel rate required by the test, and add the formats to the format knob list. To create these formats, hold down the R button while pressing and releasing the ACS button. When no analyzer is installed, the EDID-based knob list contains only standard base formats.
• Added LGRamp and Toshiba images, which are special test images based on customer specifications.

• Corrected YCbCr 4:2:2 output protocol when using double-clocked formats (for example, 480i2x29). The double-clocked format output protocol was wrong when selecting YCbCr 4:2:2 using the DVSM command. This fix requires HDMI gateware revision A or later to be installed.
• The PacketRX image (used by HDMI analyzer) is now updated in real time if any received packet changes.
• Corrected AVI "VIC" codes output with letterbox (LH) formats for the following 861B formats:

  Previous VIC code	Correct VIC code	Format Name
  3	2	480p59LH
  3	2	480p60LH
  7	6	480i2xL1
  7	6	480i2xL2
  9	8	240p2xL1
  9	8	240p2xL2
  9	8	240p2xL3
  9	8	240p2xL4
  11	10	480i4xL1
  11	10	480i4xL2
  13	12	240p4xL1
  13	12	240p4xL2
  13	12	240p4xL3
  13	12	240p4xL4
  15	14	480p2xL1
  15	14	480p2xL2
  18	17	576p50LH
  22	21	576i2xLH
  24	23	288p2xL1
  24	23	288p2xL2
  24	23	288p2xL3
  26	25	576i4xLH
  28	27	288p4xL1
  28	27	288p4xL2
  28	27	288p4xL3
  30	29	576p2xLH

• Interlaced video formats with analog or digital composite sync types 2 or 4 may be defined with an odd number of lines (VRES).

• (DVI analyzer) Corrected problem that caused pseudo random noise test to detect no input signal at any pixel rate.

• (HDMI only) Implemented the XGCP and MUTE commands.

• (HDMI only) Corrected timing error in the double clocking formats 480i and 576i. This fix also requires HDMI FPGA revision 8 or later (see GenStats images for FPGA revision).
• (HDMI only) Hot-plug signal is detected correctly.

• When using the "Hot-plug Format' special mode, or the DDC-auto configuration, the generator now uses the HDMI-LLC's 24-bit IEEE OUI registration identifier 0x000C03 to decide if the sink (receiver) is HDMI (not DVI), instead of checking for the existence of the VSBD block.
• Corrected these format definitions (previous values are in parenthesis).

Format	NCPP	HTOT	HRES	HSPD	HSPW
480p2x59	(2) 1	(858) 1716	(720) 1440	(16) 32	(62) 124
480p2x60	(2) 1	(858) 1716	(720) 1440	(16) 32	(62) 124
480p2xL1	(2) 1	(858) 1716	(720) 1440	(16) 32	(62) 124
480p2xL2	(2) 1	(858) 1716	(720) 1440	(16) 32	(62) 124
480p2xS1	(2) 1	(858) 1716	(720) 1440	(16) 32	(62) 124
480p2xS2	(2) 1	(858) 1716	(720) 1440	(16) 32	(62) 124
576p2x50	(2) 1	(858) 1716	(720) 1440	(12) 24	(64) 128
576p2xLH	(2) 1	(858) 1716	(720) 1440	(12) 24	(64) 128
576p2xSH	(2) 1	(858) 1716	(720) 1440	(12) 24	(64) 128

NCPP is the number of clocks per pixel, HTOT is the horizontal total pixels (blank + active), HRES is the horizontal active pixels, HSPD is the horizontal sync pulse delay, and HSPW is the horizontal sync pulse width.

• Firmware was changed to correct a Video Generator Manager defect related to archiving and restoring of custom objects (formats, images, test sequences) when updating firmware.

• When using HDMI or DVI outputs, the generator displays a Hot-plug: Not detected message when it cannot detect that a receiver is connected with the generator. When no receiver is detected, the generator turns off the TMDS output, as required by the DVI specification, unless the generator is in the Hot-plug Bypass mode (see next item).
• Added Hot-plug Bypass special key mode, which forces DVI or HDMI outputs to remain on even if the generator cannot detect that a receiver is connected. This feature is useful when testing receivers that do not implement the hot plug detect signal correctly. To enable the Hotplug Bypass mode, hold down the Step, R, and ASC keys while starting the generator, or send the SROP 65536 command.
• With HDMI board revision F or later (see GenStats image), the DVSS (Digital Video Signal Swing) and DVSC (Digital Video Swing Calibration factor) commands can be used to set the voltage swing between 150 and 1560 mVp-p. The DVSS value is a format parameter, which is stored with each format. The DVSC value is a system parameter that changes all formats. Examples:

  DVSS?           // Return current signal swing in volts

  DVSS 1.1        // Set digital video swing to 1100mV for current format

  DVSC 1.1; FMTU  // Multiply DVSS value for all formats by 1.1

• With HDMI board revision F or later (see GenStats image), three calibration factors (slope150, slope1000, and slope1560) have been added to control the voltage swing of the TMDS signal. These factors are the last three factors returned by the CALF? query. Each factor may be set to a value from 0 to 4095. For example, to change the voltage swing of all TMDS formats in the generator, adjust the value of the slope1000 factor.
• Added EIA0729 format (based on obsolete RS-170), which uses 1.0V for voltage level, and 0.4V for sync level.
• When using a video board with FPGA revision 107 or later (see GenStats image), the PCPG command can be used to output the pixel clock at the Special Sync BNC connector. Send the PCGP 1 command to enable this feature.

• When using the HDMI option, the coding type, sample size, and sampling frequency of the audio InfoFrame are all set to zero, and refer to the stream header as required by the HDMI specification.
• The SCPI command syntax has been corrected to confirm with the Standard Commands for Programmable Instrumentation (SCPI) standard:
  
  

  Correct syntax:	XAVI:VIC?;B?;S?
  	XAVI:VIC?;:XAVI:B?;:XAVI:S?
  Not correct (no colon after semi-colon):	XAVI:VIC?;XAVI:B?;XAVI:S?

  
  
• When using the HDMI option, images are displayed correctly when the special modes Digital Friendly, DVI (not HDMI), and HDCP tester are enabled simultaneously.
• Vertical noise no longer appears the first time the generator is started after being initialized.
• For NTSC format, HRES was changed from 720 to 710, and HDSP was changed from 16 to 20.
• For PAL format, HRES was changed from 720 to 702, and HDSP was changed from 12 to 20.

• Added PSPM (probe sync pulse mode) query and command, with the following settings:
  • 0 one pulse / frame
  • 1 one pulse every active line
  • 3 one pulse every line
• Added JDMI query and command, which is used to change the maximum and minimum pixel rates of the HDMI output.
• Added SCPI parser to enable more direct control of InfoFrame fields.
  • For the AVI InfoFrame:
    XAVI:VERS, XAVI:S, XAVI:B, XAVI:A, XAVI:Y, XAVI:R, XAVI:M, XAVI:C, XAVI:SC, XAVI:VIC, XAVI:PR XAVI:ETB, XAVI:SBB, XAVI:ELB, XAVI:SRB
  • For the Audio InfoFrame:
    XAUD:VERS, XAUD:CC, XAUD:CT, XAUD:SS, XAUD:SF, XAUD:MBR, XAUD:CA, XAUD:LSV, XAUD:DMI
  • For the mpeg InfoFrame:
    XMPG:VERS, XMPG:MB, XMPG:MF, XMPG:FR
  • For the SPD InfoFrame:
    XSPD:VERS, XSPD:VNS, XSPD:PDS, XSPD:SDI
• The TVHatch, PulseBar, TintAlgn and BurstTCE images, which were previously available with TV formats only, are now available with HDTV, digital and RGB video formats.
• Added TVoutLin image, which is similar to the Outline1 image, but uses anti-aliasing for vertical bars, and has 2-pixel wide horizontal lines to reduce flickering.

• Fixed the ANTI (anti alias) command.

• Horizontal blanking interval can be set to zero, so the HRES can be set to the same value as HTOT. This feature requires video board FPGA 91 or later.

• Corrected red and blue color reversal on TV output. This fix requires video board FPGA 91 or later.
• Corrected noise that appears along left side of the image, particularly animated images. This fix requires video board FPGA 91 or later.

• Corrected bug that caused generator to re-initialize itself.

• Updated to support gateware version 5 on HDMI option.

• Added DVSS command and query, which controls the TMDS signal swing from 0.0 to 2.0 volts differential peak-to-peak (nominally 1.000, 0.150 to 1.560 range guaranteed). Currently, the DVSS command is supported only by HDMI boards revision C or later. To determine the HDMI board revision in your generator, view the GenStats image.

• Added PacketTX image, which is available with HDMI option only. The PacketTx image displays the content of InfoFrames (AVI, AUD, SPD, MPEG, GIF and other packets) sent by the HDMI transmitter. See the HDMI manual (update available soon) for information about how to modify the default InfoFrames, using the Data (Island) Packets Generator and the InfoFrame Generator commands. (The PacketRx image is reserved for future use.)
• Generators with a DVI or HDMI output now support a "hot-plug formats" special mode, which configures the Format knob to list only formats reported by the EDID structure from the connected DVI or HDMI display. This format knob list is created automatically when a DVI or HDMI display is connected with the generator. To active this mode, hold down R and ASC while starting the generator, or use the SROP 16384 command. To switch between the EDID-based knob list and the standard knob list, hold down the R button while pressing and releasing the ACS button.

  When the generator is connected with a DDC-compliant analog display, holding down R while pressing and releasing the ACS button configures the knob list for the display.

• Added AFDtest image, which work in analog and digital modes. The AFDtest image demonstrates different aspect ratios and content maps. See the HDMI manual (update available soon) for more information.
• Added PixelRep image, which works with EIA/CEA-861B formats in both analog and digital modes. The PixelRep image can be used to apply pixel repetiton after the format is loaded. Use the image to vary the number of pixels-per-pixel to render the image with repeated pixels for test purposes. For more information about pixel repetition, see the EIA/CEA-861B standard.
• The EdidData image now reads and parses the first timing extension block.

• Analog, digital, and TV ouputs now support 24-bit TrueColor, up to 80 MHz pixel rate for analog and digital outputs. To toggle between 8-bit and 24-bit color, hold the R button, and press the B button.
• When the generator is configured to use the Enable status display mode, the letter T (TrueColor) left of the format name indicates that 24-bit color depth is selected. A number 8 indicates that 8-bit color depth is selected.
• Digital output supports double clocking 2x at 8 and 24 bits per pixel, at 13.5 MHz to 80 MHz for DVI, and 13.5 MHz to 40 MHz for HDMI.
• Generator can load an 8-bit or 24-bit bitmap image directly from a PC card, without downloading the image from the PC (instructions)
• When using analog HDTV formats with tri-level sync type, the TSPG command and query can toggle between tri-level and bi-level syncs. The Bilevel, Trilevel Toggle key operation can also be used to toggle the tri-level and bi-level sync types (see the GenOps image for instructions).
  
  
• New Austrailian formats:
  
  

  576i50	SD @ 100Hz field rate HRAT=31250 VTOT=625 SCAN=2
  1152iSH	AS 4933.1-200X (8/5 vertical scope 720 to 1152)
  1152iSH_	1152iSH at harmonic of SMPTE 274M 148.5MHz
  1152iLH	AS 4933.1-200X (6.7% letterbox 1080 in 1152)
  1152iLH_	1152iLH at harmonic of SMPTE 274M 148.5MHz
  576i50WL	SD letterboxed in 576i50W
  576i50_L	576i50WL at harmonic of SMPTE 274M 148.5MHz
  576i50WH	HD @ 100Hz field rate HRAT=31250 VTOT=625 SCAN=2
  576i50_H	576i50WH at harmonic of SMPTE 274M 148.5MHz
  576pWL	SD letterboxed in 576pWH
  576pWL_	576iWL at harmonic of SMPTE 274M 148.5MHz
  576pWH_	576pWH at harmonic of SMPTE 274M 148.5MHz
  1152iLA	SD 2/1 vertical scope 576 to 1152 & letterboxed in 1188
  1152iLA_	1152iLA at harmonic of SMPTE 274M 148.5MHz

  
  
  
• Added PRN24bit image, which can be used as an external source of psuedo random noise at different resolutions, by the DVI analyzer. The PRN24bit image assumes 24 bits per pixel, and fills the active area with psuedo random noise pixels generated using the QDI-BCM algorithm, which is based on the Broadcom algorithm.

• The Infocus1 image now draws full red, gren, blue and gray ramps when in 24-bit TrueColor mode.
• The DDC auto-configuration (toggling R and ACS keys) now creates a format knob list that has all the detailed timings supported in the EDID data of the receiver. Previously, only the first timing was added to the knob list.
• Digital-friendly mode is supported on generators with an LVDS daughter card.
• PAl is now calibrated before NTSC.

• The receiver on the optional DVI analyzer now supports CEA-861 EDID timing extension version 1, which has two, 128-btye blocks. Below are supported formats.

  Standard VESA formats:

  • 720 x 400 @ 70Hz IBM0770H @ 28.40 Mpixel
  • 720 x 400 @ 88Hz XGA2 @ 35.50 Mpixel
  • 640 x 480 @ 60Hz DMT0660 @ 25.20 Mpixel
  • 640 x 480 @ 67Hz APP0667 @ 31.30 Mpixel
  • 640 x 480 @ 72Hz DMT0672 @ 31.50 Mpixel
  • 640 x 480 @ 75Hz DMT0675 @ 31.50 Mpixel
  • 800 x 600 @ 56Hz DMT0856 @ 36.00 Mpixel
  • 800 x 600 @ 60Hz DMT0860 @ 40.00 Mpixel
  • 800 x 600 @ 72Hz DMT0872 @ 50.00 Mpixel
  • 800 x 600 @ 75Hz DMT0875 @ 49.50 Mpixel
  • 832 x 624 @ 75Hz APP0875 @ 55.00 Mpixel
  • 1024 x 768 @ 87Hz DMT1043 @ 44.90 Mpixel
  • 1024 x 768 @ 60Hz DMT1060 @ 65.00 Mpixel
  • 1024 x 768 @ 70Hz DMT1070 @ 75.00 Mpixel
  • 1024 x 768 @ 75Hz DMT1075 @ 78.75 Mpixel
  • 1280 x 1024 @ 75Hz DMT1275G @ 135.0 Mpixel
  • 1152 x 870 @ 75Hz APP1175 @ 100.0 Mpixel

  Detailed timings:

  • 1600 x 1200 @ 60Hz DMT1660 @ 162 Mpixelz
  • 1280 x 1024 @ 60Hz VSC1260G @ 108 Mpixel

  EIA/CEA-861-B formats:

  • 720x480 progressive at 59.94Hz and 27Mhz and 4:3
  • 720x480 progressive at 59.94Hz and 27MHz and 16:9
  • 1280x720 progressive at 50Hz and 74.25MHz and 16:9
  • 1280x720 progressive at 60Hz and 74.25MHz and 16:9
  • 1920x1080 interlace at 50Hz and 74.25Mhz and 16:9
  • 1920x1080 interlace at 60Hz and 74.25MHz and 16:9
  
  
• The receiver on the optional HDMI analyzer now supports CEA-861 EDID timing extension version 2, which has two, 128-byte blocks. Below are the formats supported.

  Standard VESA formats:

  • 720 x 400 @ 70Hz IBM0770H @ 28.40 Mpixel
  • 720 x 400 @ 88Hz XGA2 @ 35.50 Mpixel
  • 640 x 480 @ 60Hz DMT0660 @ 25.20 Mpixel
  • 640 x 480 @ 67Hz APP0667 @ 31.30 Mpixel
  • 640 x 480 @ 72Hz DMT0672 @ 31.50 Mpixel
  • 640 x 480 @ 75Hz DMT0675 @ 31.50 Mpixel
  • 800 x 600 @ 56Hz DMT0856 @ 36.00 Mpixel
  • 800 x 600 @ 60Hz DMT0860 @ 40.00 Mpixel
  • 800 x 600 @ 72Hz DMT0872 @ 50.00 Mpixel
  • 800 x 600 @ 75Hz DMT0875 @ 49.50 Mpixel
  • 832 x 624 @ 75Hz APP0875 @ 55.00 Mpixel
  • 1024 x 768 @ 87Hz DMT1043 @ 44.90 Mpixel
  • 1024 x 768 @ 60Hz DMT1060 @ 65.00 Mpixel
  • 1024 x 768 @ 70Hz DMT1070 @ 75.00 Mpixel
  • 1024 x 768 @ 75Hz DMT1075 @ 78.75 Mpixel
  • 1280 x 1024 @ 75Hz DMT1275G @ 135.0 Mpixel
  • 1152 x 870 @ 75Hz APP1175 @ 100.0 Mpixel

  Detailed timings:

  • 1920x1080 interlace at 60 Hz and 74.25 MHz 16:9
  • 720x480 progressive at 59.94Hz and 27.00 MHz 4:3

  EIA/CEA-861-B formats:

  • 1280 X 720 P 59.94/60Hz 16:9
  • 640 X 480 P 59.94/60Hz 4:3
  • 720 X 480 P 59.94/60Hz 16:9
  • 720(1440) X 480 I 59.94/60Hz 4:3
  • 1720(1440) X 480 I 59.94/60Hz 16:9
  • DTV (Basic Audio)
  • YCbCr (4:4:4)
  • YCbCr (4:2:2)

  Video Short Block Description:

  • 1920 X 1080 I 59.94/60Hz 16:9 Native Mode
  • 720 X 480 P 59.94/60Hz 4:3
  • 720 X 480 P 59.94/60Hz 16:9
  • 1280 X 720 P 59.94/60Hz 16:9
  • 640 X 480 P 59.94/60Hz 4:3
  • 720(1440) X 480 I 59.94/60Hz 4:3
  • 720(1440) X 480 I 59.94/60Hz 16:9
  
  
  
• The generator now tests PCMCIA SRAM cards before writing data. If the card is bad, Card is bad is displayed for 3 seconds.
• The EdidData image displays the hex sheet for the two blocks in case there is an extension block. Also, in case the check sum is bad, the EdidData image displays the check sum value that should be used.
• Added -4% gray level to the SMPTEbar image.
• Added commands to read/write through the i2c buss from the receiver on the HDMI analyzer.

  The test command/query is as follows:

  i2cr? tmdsRx i2c_addr reg_offset num_of_bytes

  i2cw tmdsRx i2c_addr reg_offset num_of_bytes [data is ASCII hex char]

  The read/write control of the transmitter works as follows:

i2cr? tmds i2c_addr reg_offset num_of_bytes

i2cw tmds i2c_addr reg_offset num_of_bytes [data is ASCII hex char]

• The "passed" message used with HDCP images now displays in the correct font.
• Corrected analog output level of the red color when the AVSS command is used to control the voltage levels of the colors.
• Corrected errors reported by the DeltaErr image on the DVI analyzer when using format TEST165.
• VGM 3.01 does not recognize some format parameters, including the digital video quantization modes (DVQM), and the number of bits per color component (NBPC). Using VGM to edit a TV format could cause the DVQM and NBPC parameters to be set to wrong values when the format is saved in the generator. These parameters are now stored correctly, and are not changed by VGM.
• Corrected low DVI output voltage level with HDCP images on generators with a BroadCom transmitter.

• Added two new patterns to graphics library. trump1 has the following repeated pattern:
  

  1010
  1010
  0101
  0101
  

  trump2 has the following repeated pattern:

  1010
  0101
  0101
  1010
  

• Added HalfClk image, which has alternating values of pixels with colors (R=1, G=1, B=1) and (R=255, G=255, B=255). This image generates square signals at half pixel rate at the DVI outputs.
• Digitial friendly mode is allowed only if the generator has the digital option.

• Reduced size of moving boxes in the persist image.
• Centered text in the GenStats and GenOps images.

• Added commands that read and write control signals for DVI transmitters.

  Quantum Data digital generators use either a BCM7500 (BroadCom) or a Sil 170B (pin compatible with Sil 168) DVI transmitter. Control signals for the BCM7500 and the Sil 170B transmitters are defined differently. To identify the transmitter in your generator, load the GenStats image. If DVI (SII) is displayed under Options, the generator has an Sil 170B transmitter. If DVI is displayed, the generator has a BCM7500 transmitter.

  The SCTL command sets the control signals of the DVI transmitter to HIGH. The RCTL command resets the control signals of the transmitter to LOW.

  The SCTL? and RCTL? queries read the status of the control signals from generators with an Sil 170B transmitter. You cannot read the status of the control signals from a BCM7500 transmitter.

  The BCM7500 has 8 dedicated pins for these control signals, 4 pins for each link. CTL00 (pin 96), CTL01 (pin 93), CTL02 (pin 92), and CTL03 (pin 91) are used for link zero. Also, CTL10 (pin 75), CTL11 (pin 74), CTL12 (pin 71) and CTL13 (pin 70) are used for link one.

  The SCTL and RCTL commands take one parameter, a single byte in hex. Each bit corresponds to a control pin, making the value a mask. The least significant bit is associated with CTL00, and the most significant bit with CTL13. The SCTL command sets the bit with value "1" to HIGH. The RCTL command sets the bit with value "1" to LOW.

  The mask is as follows:

  [CTL13 CTL12 CTL11 CTL10 CTL03 CTL02 CTL01 CTL00]

  Examples for BCM7500 transmitter:

  • Set only CTL01 and CTL11 pins to HIGH:

  R:\>SCTL 22

  • Set only CTL02 and CTL10 pins to HIGH:

  R:\>SCTL 14

  • Reset only CTL02 and CTL10 pins back to LOW:

  R:\>RCTL 14

  • Reset CTL00 and CTL12 pins back to LOW:

    R:\>RCTL 41

    Note that CTL03 and CTL13 are not affected by these commands since these two pins are used for HDCP control.

An Sil 170B transmitter has two control signals, CTL1 and CTL2, which are controlled through the I²C bus on the Sil 170B. The commands described above can also control these signals by using the least significant 2 bits in the byte, and ignoring the other bits.

Examples for Sil 170B transmitter:

• Set CTL1 to HIGH:

R:\>SCTL 01

• Set CTL2 to HIGH:

R:\>SCTL 02

• Set both CTL1 and CTL2 to HIGH:

R:\>SCTL 03

• Reset CTL2 to LOW:

R:\>RCTL 02

For the SiI 170B, use the RCTL? or SCTL? query to read the status of these two signals.

After running the commands above, the following query would return 01:

R:\>RCTL?

• Added support for reading the enhanced display data channel (DDC) using the I²C bus. All parameters are hex values.

  i2cr? e_ddc ddc_addr1 segment_num ddc_addr2 offset bytes

  This example returns the 128 bytes of Extended Display Identification Data (EDID) data from the monitor:

  i2cr? e_ddc 60 0 a0 0 80

• Corrected noise in the TV format and other formats with low pixel rates.
• Added support for new Quantum Data video standards.
• For the DDC auto-configuration, the format created from the first detailed timing is now assigned the gamma, sync swing, and video swing values from the EDID data. Previously, it was set to no gamma, and the swings were 700mV and 300mV. The vertical total also has been corrected for interlace formats, since the EDID detailed timing returns the values for one field while the format requires the values for one frame (for example, two fields).
• Added standard colors gray -2% and gray -4%, which are blacker than black. The SMPTEbar image uses these colors.
• The GraysAll image now displays the gray level.

• Added support for 400MHz.

• Corrected missing right side of image in TV output for video boards with FPGA revision 77 or less. This problem was corrected in FPGA revision 78.

Initial release of 802R.

• Contact Quantum Data Support
• Product updates