Summary of Results

Pass	Test Name	Spec Range	Measured Value	Margin
	Clock Jitter	<= 250mTbit	99mTbit	60.4 %
	Mask Test	Zero Mask Failures	0.000	N/A
	Data Jitter	<=0.3Tbit	145m	51.7 %
	Clock Rise Time	>= 75.000ps	84.850ps	13.1 %
	Clock Fall Time	>= 75.000ps	83.710ps	11.6 %
	Data Lane A Rise Time	>= 75.000ps	90.041ps	20.1 %
	Data Lane A Fall Time	>= 75.000ps	99.383ps	32.5 %
	Clock - Overshoot	<=15%	6.267	58.2 %
	Clock - Undershoot	<=25%	5.467	78.1 %
	Data Lane A - Overshoot	<=15%	5.000	66.7 %
	Data Lane A - Undershoot	<=25%	12.715	49.1 %
	Clock Duty Cycle(Minimum)	>=40%	51.010	27.5 %
	Clock Duty Cycle(Maximum)	<=60%	51.510	14.2 %

Report Detail

Clock Jitter Reference: HDMI CTS 1.1,Test ID 7-9

Trial Summary

P/F	Trial #	Actual Value	Margin	Test Frequency(MHz)	# Edges	Tbit(ps)	Clock Jitter(ps)
	Trial 1	99mTbit	60.4	148.347	16.00000M	674.094	66.650
	Trial 2	89mTbit	64.4	148.513	16.00000M	673.342	59.910
	Trial 3	97mTbit	61.2	148.391	16.00000M	673.897	65.150

Trial 1: Clock Jitter

Trial 2: Clock Jitter

Trial 3: Clock Jitter

Mask Test Reference: HDMI CTS 1.1,Test ID 7-10

Test Summary: Pass Test Description: For all channels under all operating conditions specified in Table 4-11 . The Source shall have output levels at TP1, which meet the normalized eye diagram requirements.
Test Limits:Zero Mask Failures# Mask Failures (worst of 3)0.000

Result Details:

Trial Summary

P/F	Trial #	Actual Value	Margin	Maximum Margin	Data Lane A	Test Frequency(MHz)	Mask Moved(ps)	# Acquisitions Point	Tbit(ps)	RightJitterData(Tbit)	LeftJitterData(Tbit)	RightJitterData(ps)	LeftJitterData(ps)	Differential Swing Voltage(mV)
	Trial 1	0.000	N/A	0.000000s	D0	148.347	0.000	16.00000M	673.417	145m	145m	97.500	97.500	800.000
	Trial 2	0.000	N/A	0.000000s	D0	148.513	0.000	16.00000M	673.381	138m	138m	93.000	93.000	800.000
	Trial 3	0.000	N/A	0.000000s	D0	148.391	0.000	16.00000M	673.414	143m	145m	96.000	97.500	800.000
	Mean	0.000		0.000
	StDev	0.000		0.000
	Range	0.000		0.000
	Min	0.000		0.000
	Max	0.000		0.000

# Mask Failures

Trial 1: # Mask Failures

Trial 2: # Mask Failures

Trial 3: # Mask Failures

Data Jitter Reference: HDMI CTS 1.1,Test ID 7-10

Test Summary: Pass Test Description: For all channels under all operating conditions specified in Table 4-11 . The Source shall have output levels at TP1, which meet the normalized eye diagram requirements.
Test Limits:<=0.3TbitTbitCheck (worst of 3)145m

Result Details:

Trial Summary

P/F

Trial #

Actual Value

Margin

Data Lane A

Test Frequency(MHz)

Mask Moved(ps)

# Acquisitions Point

Tbit(ps)

RightJitterData(Tbit)

LeftJitterData(Tbit)

RightJitterData(ps)

LeftJitterData(ps)

Differential Swing Voltage(mV)

Trial 1

145m

51.7

D0

148.347

0.000

16.00000M

673.417

145m

145m

97.500

97.500

800.000

Trial 2

138m

54.0

D0

148.513

0.000

16.00000M

673.381

138m

138m

93.000

93.000

800.000

Trial 3

145m

51.7

D0

148.391

0.000

16.00000M

673.414

143m

145m

96.000

97.500

800.000

TbitCheck

Trial 1: TbitCheck

Trial 2: TbitCheck

Trial 3: TbitCheck

Clock Rise Time Reference: HDMI CTS 1.1,Test ID 7-4

Test Summary: Pass Test Description: The transition time is defined as the time interval between the normalized 20% and 80% amplitude levels. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Test Limits:VALUE >= 75.000psRaw clock transition time (worst of 3)84.850ps

Result Details:

Trial Summary

P/F	Trial #	Actual Value	Margin	Test Frequency(MHz)	Upper Threshold(%)	Lower Threshold(%)	# Edges
	Trial 1	85.070ps	13.4	148.347	80.000	20.000	7.610000k
	Trial 2	84.850ps	13.1	148.513	80.000	20.000	7.610000k
	Trial 3	85.820ps	14.4	148.391	80.000	20.000	7.610000k

Raw clock transition time

Trial 1: Raw clock transition time

Trial 2: Raw clock transition time

Trial 3: Raw clock transition time

Clock Fall Time Reference: HDMI CTS 1.1,Test ID 7-4

Test Summary: Pass Test Description: The transition time is defined as the time interval between the normalized 20% and 80% amplitude levels. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Test Limits:VALUE >= 75.000psRaw clock transition time (worst of 3)83.710ps

Result Details:

Trial Summary

P/F	Trial #	Actual Value	Margin	Test Frequency(MHz)	Upper Threshold(%)	Lower Threshold(%)	# Edges
	Trial 1	83.710ps	11.6	148.347	80.000	20.000	7.610000k
	Trial 2	84.790ps	13.1	148.513	80.000	20.000	7.610000k
	Trial 3	84.010ps	12.0	148.391	80.000	20.000	7.610000k

Raw clock transition time

Trial 1: Raw clock transition time

Trial 2: Raw clock transition time

Trial 3: Raw clock transition time

Data Lane A Rise Time Reference: HDMI CTS 1.1,Test ID 7-4

Test Summary: Pass Test Description: The transition time is defined as the time interval between the normalized 20% and 80% amplitude levels. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Test Limits:VALUE >= 75.000psTransition Time (worst of 3)90.041ps

Result Details:

Trial Summary

P/F	Trial #	Actual Value	Margin	Test Frequency(MHz)	Data Lane A	Upper Threshold(%)	Lower Threshold(%)	#Edge
	Trial 1	90.041ps	20.1	148.347	D0	80.000	20.000	1.000000k
	Trial 2	93.760ps	25.0	148.513	D0	80.000	20.000	1.000000k
	Trial 3	91.788ps	22.4	148.391	D0	80.000	20.000	1.000000k

Histogram

Trial 1: Histogram

Trial 2: Histogram

Trial 3: Histogram

Transition Time

Trial 1: Transition Time

Trial 2: Transition Time

Trial 3: Transition Time

Data Lane A Fall Time Reference: HDMI CTS 1.1,Test ID 7-4

Test Summary: Pass Test Description: The transition time is defined as the time interval between the normalized 20% and 80% amplitude levels. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Test Limits:VALUE >= 75.000psTransition Time (worst of 3)99.383ps

Result Details:

Trial Summary

P/F	Trial #	Actual Value	Margin	Test Frequency(MHz)	Data Lane A	Upper Threshold(%)	Lower Threshold(%)	#Edge
	Trial 1	99.383ps	32.5	148.347	D0	80.000	20.000	1.000000k
	Trial 2	103.200ps	37.6	148.513	D0	80.000	20.000	1.000000k
	Trial 3	103.100ps	37.5	148.391	D0	80.000	20.000	1.000000k

Histogram

Trial 1: Histogram

Trial 2: Histogram

Trial 3: Histogram

Transition Time

Trial 1: Transition Time

Trial 2: Transition Time

Trial 3: Transition Time

Clock - Overshoot Reference: HDMI CTS 1.1,Test ID 7-5

Test Summary: Pass Test Description: TMDS overshoot must be below 15% of 2*VSWING. For compliance, the DUT should output the lowest supported pixel clock frequency during the test.
Test Limits:<=15%Overshoot (worst of 3)6.267

Result Details:

Trial Summary

P/F	Trial #	Actual Value	Margin	Test Frequency(MHz)	# Edges	Differential Swing Voltage(mV)	VH(mV)	VL(mV)	VH+(mV)	VH+(%)	VL-(mV)	VL-(%)
	Trial 1	6.267	58.2	148.347	1.000000k	750.000	380.000	-370.000	44.000	5.867	47.000	6.267
	Trial 2	5.459	63.6	148.513	1.000000k	751.000	380.000	-371.000	41.000	5.459	36.000	4.794
	Trial 3	5.578	62.8	148.391	1.000000k	753.000	383.000	-370.000	39.000	5.179	42.000	5.578

VH, VH+, VH-

Trial 1: VH, VH+, VH-

Trial 2: VH, VH+, VH-

Trial 3: VH, VH+, VH-

VL, VL+, VL-

Trial 1: VL, VL+, VL-

Trial 2: VL, VL+, VL-

Trial 3: VL, VL+, VL-

Clock - Undershoot Reference: HDMI CTS 1.1,Test ID 7-5

Test Summary: Pass Test Description: TMDS undershoot must below 25% of 2*VSWING. For compliance, the DUT should output the lowest supported pixel clock frequency during the test.
Test Limits:<=25%Undershoot (worst of 3)5.467

Result Details:

Trial Summary

P/F	Trial #	Actual Value	Margin	Test Frequency(MHz)	# Edges	Differential Swing Voltage(mV)	VH(mV)	VL(mV)	VH-(mV)	VH-(%)	VL+(mV)	VL+(%)
	Trial 1	5.467	78.1	148.347	1.000000k	750.000	380.000	-370.000	41.000	5.467	36.000	4.800
	Trial 2	3.196	87.2	148.513	1.000000k	751.000	380.000	-371.000	24.000	3.196	23.000	3.063
	Trial 3	3.453	86.2	148.391	1.000000k	753.000	383.000	-370.000	26.000	3.453	21.000	2.789

VH, VH+, VH-

Trial 1: VH, VH+, VH-

Trial 2: VH, VH+, VH-

Trial 3: VH, VH+, VH-

VL, VL+, VL-

Trial 1: VL, VL+, VL-

Trial 2: VL, VL+, VL-

Trial 3: VL, VL+, VL-

Data Lane A - Overshoot Reference: HDMI CTS 1.1,Test ID 7-5

Test Summary: Pass Test Description: TMDS overshoot must be below 15% of 2*VSWING. For compliance, the DUT should output the lowest supported pixel clock frequency during the test.
Test Limits:<=15%Overshoot (worst of 3)5.000

Result Details:

Trial Summary